イグチ　ユキヒロ   Iguchi Yukihiro   井口　幸洋    所属   明治大学  理工学部    職種   専任教授
言語種別	英語
発行・発表の年月	2006/03
形態種別	学術雑誌
標題	A design of AES encryption circuit with 128-bit keys using look-up table ring on FPGA
執筆形態	共著(筆頭者以外)
掲載誌名	IEICE Trans. on Information and Systems
巻・号・頁	E89-D(3),pp.pp. 1139 - 1147
著者・共著者	H. Qin, T. Sasao and Y. Iguchi
概要	This paper addresses a pipelined partial rolling (PPR) architecture for the AES encryption. The key technique is the PPR architecture. With the proposed architecture on the Altera Stratix FPGA, two PPR implementations achieve 6.45 Gbps throughput and 12.78 Gbps throughput, respectively. Compared with the unrolling implementation that achieves a throughput of 22.75 Gbps on the same FPGA, the two PPR implementations improve the memory efficiency (i.e.，throughput divided by the size of memory for core) by 13.4% and 12.3%，respectively，and reduce the amount of the memory by 75% and 50%，respectively. Also, the PPR implementation has a up to 9.83％higher memory efficiency than the fastest Previous FPGA implementation known to date. In terms of resource efficiency (i.e., throughput divided by the equivalent logic element or slice), one PPR implementation offers almost the same as the rolling implementation, and the other PPR implementation offers a medium value between the rolling implementation and the unrolling implementation that has the highest resource efficiency. However, the two PPR implementations can be implemented on the minimum-sized Stratix FPGA while the unrolling implementation cannot. The PPR architecture fills the gap between unrolling and rolling architectures and is suitable for small and medium-sized FPGAs.