Faculty Database - Yamazaki Koji

Books and Papers

Conference Presentations

Academic Qualifications

Academic Associations Membership

Research Topics, Consignment Studies & KAKENHI Researches

Current Specialized Field

（Last updated : 2015-02-14 17:08:05.607）

Yamazaki Koji
Department Undergraduate School , School of Information and Communication

Position Associate Professor

■ Books and Papers

1.	2011/01	Article	Fault Diagnosis for Logic Circuits - Development of Methods for Identifying Fault Locations based on Output Responses - pp.266-279 (Collaboration)
2.	2010/11	Article	A Method for Locating Open Faults by Using a Fault Excitation Function pp.2416-2425 (Collaboration)
3.	2009/01	Article	A Novel Approach for Improving the Quality of Open Fault Diagnosis VLSI Design pp.85-90 (Collaboration)
4.	2008/03	Article	A Method of Locating Open Faults on Incompletely Identified Pass/Fail Information IEICE,Trans.Information and Systems E91-D(3),pp.661-666 (Collaboration)
5.	2006/11	Article	Fanout-Based Fault Diagnosis for Open Faults On Pass/Fail Information IEEE computer society Proc.of 15th ATS pp.349-353 (Collaboration)
6.	2005/11	Article	Post-BIST Fault Diangosis for Multiple Stuck-at Faults Proc. IEEE International Silicon Debug and Diaganosis pp.1-6 (Collaboration)
7.	2005/05	Article	On the fault diagnosis in the presence of unknown fault models usign pass/fail infomation IEEE International Symposium on Circuits and System ISCAS2005 pp.2987-2990 (Collaboration)
8.	1999/11	Article	Identification of Redundant Crosspoint Faults in Sequential PLAs with Fault-Free Hardware Reset IEEE Computer Society, Proc. of 8th ATS pp.269-274 (Collaboration)
9.	1997/11	Article	An Approach to Diagnose Logical Faults in Partially Observable Sequential Circuits IEEE Computer Society, Proc. of 6th ATS pp.168-173 (Collaboration)
10.	1994/11	Article	An approach of diagnosing single bridging faults in CMOS combinational circuits IEEE computer societyProc.of 3rd ATS pp.88-93 (Collaboration)
11.	1993/07	Article	SIFLAP-G:A method of diagnosing gate-level faults in combinational circuits IEICE Trans. Inf. & syst. E76-D,pp.826-831 (Collaboration)
12.	1992/11	Article	A method of diagnosing logical faults in commbinational circuits IEEE computer societyProc.of 1st ATS pp.170-175 (Collaboration)
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■ Conference Presentations

1.	1995/11	A simple technique for locating gate-level faults in CMOS combinational circuits (4th Asian Test Symposium)
2.	1995/11	A simple technique for locating gate-level faults in combinational circuits (IEEE computer societyProc.of 4th ATS)

■ Academic Qualifications

1.	～1994/03	〔Doctorial Course〕 Electrical Engineering, Graduate School, Division of Engineering, Meiji University, Completed,
2.	～1991/03	〔Master Course〕 Electrical Engineering, Graduate School, Division of Engineering, Meiji University, Completed,

■ Academic Associations Membership

IEEE

■ Research Topics, Consignment Studies & KAKENHI Researches

1.	2009～2011	Fault location for partially open faults (Key Word : VLSI, fault location, partially open faults, small delay faults)
2.	2006～2008	Fault location for open faults (Key Word : VLSI, fault location, open fault)
3.	2003～2005	Fault location under BIST environment (Key Word : VLSI,BIST,fault location)
4.	1999	Fault locaiont for delay faults on VLSI (Key Word : VLSI,delay faults,falut location)
5.	1994	Fault location for logical faults on VLSI (Key Word : VLSI,logical faults,fault location)

■ Current Specialized Field

Others