Faculty Database - Iguchi Yukihiro

Books and Papers

Conference Presentations

Academic Qualifications

Career History

Internal Committee Positions

Major Subjects

Academic Associations Membership

Research Topics, Consignment Studies & KAKENHI Researches

Exhibitions, Concerts & Competitions

Current Specialized Field

（Last updated : 2023-10-24 00:57:17）

Iguchi Yukihiro
Department Undergraduate School , School of Science and Technology

Position Professor

■ Books and Papers

1.	2021/08	Article	Classification functions for handwritten digit recognition IEICE Transactions on Information and Systems E104-D(8),pp.1076-1082 (Collaboration)
2.	2021/05	Book	A design method for multiclass classifiers Proc. of Int'l Symposium on Multiple Valued Logic pp.148-153 (Collaboration)
3.	2021/05	Book	An improved SAT-based ESOP minimizer: A list of simplified ESOPs for 8-variable symmetric functions Note of Reed-Muller Workshop (Collaboration)
4.	2020/11	Article	Handwritten digit recognition based on classification functions Proc. of Int'l Symposium on Multiple-Valued Logic pp.130-136 (Collaboration)
5.	2019/06	Book	On irreducible index generation functions Proc. of 28th International Workshop on Logic and Synthesis (Collaboration)
6.	2019/04	Book	Logic minimizers for partially defined functions Proc. of DATE 2019 (Collaboration)
7.	2018/03	Book	A Method to identify affine equivalence classes of logic functions Proc. of The 21st Workshop on Synthesis And System Integration of Mixed Information Technologies (Collaboration)
8.	2017/04	Book	An algorithm to find optimum support-reducing decompositions for index generation functions Proc. of Design Automation and Test in Europe-2017 pp.812-817 (Collaboration)
9.	2016/10	Book	A heuristic decomposition of index generation functions with many variables Proc. of　SASIMI-2016 (Collaboration)
10.	2014/12	Article	A Method to find linear decompositions for incompletely specified index generation functions using difference matrix IEICE Transactions on Fundamentals of Electronics, Communication and Computer Sciences E97-A(12),pp.2427-2433 (Collaboration)
11.	2014/05	Book	A lower bound on the number of variables to represent incompletely specified index generation functions Proc. of Int'l Symposium on Multiple Valued Logic-2014 pp.7-12 (Collaboration)
12.	2013/10	Book	A heuristic method to find linear decompositions for incompletely specified index generation functions The 18th workshop on Synthesis and system Integration of Mixed Information Technologies (SASIMI-2013 pp.143-148 (Collaboration)
13.	2013/10	Article	A Hardware Generator for Aesthetic Nonlinear Filter Banks The 18th workshop on Synthesis and system Integration of Mixed Information Technologies pp.140-141 (Collaboration)
14.	2013/05	Article	A Method of Selecting Radices for Non-binary Successive Approximation A/D Converters Workshop notes of 22nd International Workshop on Post-Binary ULSI Systems pp.76-77 (Collaboration)
15.	2012/11	Article	A realization method of fast and dependable programmable logic controllers Proc. of WRTLT'12 (Collaboration)
16.	2011/05	Article	A realization method of forward converters from multiple-precision binary numbers to residue numbers with arbitrary mutable modulus Multiple-Valued Logic (ISMVL), 2011 41st IEEE International Symposium on pp.268 - 273 (Collaboration)
17.	2010/10	Article	Development of nonlinear filter bank system for real-time beautification of facial video using GPGPU Proc. of IEEE 10th Int'l Symposium on Communications and Information Technologies pp.18-23 (Collaboration)
18.	2010/09	Article	A realization method of fast programmable logic controllers Notes of SEAA2010/DSD2010 Work in Progress Session pp.3-4 (Collaboration)
19.	2010/09	Article	A realization method of forward converters from multiple-precision binary numbers to residue numbers with arbitrary modulus Notes of SEAA2010/DSD2010 Work in Progress Session pp.1-2 (Collaboration)
20.	2008/09	Article	On the complexity of single-digit error detection function in redundant residue number system Proc. of 10th EUROMICRO Conference on Digital System Design, Architectures, Methods and Tools (Collaboration)
21.	2007/11	Article	On designs of radix converters using arithmetic decompositions Journal of Multiple-Valued Logic 13(4-6),pp.503-520 (Collaboration)
22.	2007/06	Article	Design methods of radix converters using arithmetic decompositions IEICE Trans. on Information and Systems E90-D(6),pp.905-914 (Collaboration)
23.	2007/05	Article	On designs of radix converters using arithmetic decompositions IEEE, Proc. of 37th Int'l Symposium on Multiple-Valued Logic (ISMVL-2007) (Collaboration)
24.	2006/05	Article	On designs of radix converters using arithmetic decompositions IEEE Proc. of ISMVL-2006 (Collaboration)
25.	2006/04	Article	A memory-based programmable logic device using look-up table cascade with synchronous static random access memories Japanese Journal of Applied Physics 45(4B),pp.3295-3300 (Collaboration)
26.	2006/03	Article	A design of AES encryption circuit with 128-bit keys using look-up table ring on FPGA IEICE Trans. on Information and Systems E89-D(3),pp.pp. 1139 - 1147 (Collaboration)
27.	2005/09	Article	LUT cascades and emulators for realizations of logic functions Proc. of RM2005 (Collaboration)
28.	2005/09	Article	On LUT cascade realizations of FIR filters Proc of Digital System Design (DSD) 2005 (Collaboration)
29.	2005/05	Article	Hardware to compute Walsh coefficients Proc. of IEEE International Symposium on Multiple-Valued Logic-2005 (Collaboration)
30.	2005/04	Article	An FPGA design of AES encryption circuit with 128-bit keys Proc. of GLSVLSI 2005 pp.147-151 (Collaboration)
31.	2005/04	Article	Programmable logic device with an 8-stage cascade of 64K-bit asynchronous SRAMs Cool Chips VIII, IEEE Symposium on Low-Power and High-Speed Chips (Collaboration)
32.	2004/12	Article	A realization of multiple-output functions by a look-up table ring," IEICE Transactions on Fundamentals of Electronics IEICE Transactions on Fundamentals of Electronics E87-A(12),pp.3141-3150 (Collaboration)
33.	2004/07	Article	Realization of sequential circuits by look-up table ring Proc of IEEE International Midwest Symposium on Circuits and Systems (MWSCAS 2004) (Collaboration)
34.	2004/05	Article	A method to evaluate logic functions in the presence of unknown inputs using LUT cascades, IEEE Proc. of 34th International Symposium on Multiple-Valued Logic pp.pp.302--308 (Collaboration)
35.	2004/04	Article	Fault diagnosis for RAMs using Walsh spectrum IEICE Trans. Information and Systems, E87-D(No.3) (Collaboration)
36.	2003/03	Article	Fault diagnosis for RAMs using Walsh spectrum Note of 6th International Symposium on Representations and Methodology of Future Computing Technologies (Reed-Muller 2003)
37.	2003/01	Article	Evaluation of multiple-output logic functions using decision diagrams Proc. of ASP-DAC 2003, (Asia and South Pacific Design Automation Conference 2003), (Collaboration)
38.	2002/12	Article	A design method for irredundant cascades Proc. of International Symposium on New Paradigm VLSI Computing, Sendai (Collaboration)
39.	2002/12	Article	Bi-partition of shared binary decision diagrams IEICE Transactions on Fundamentals of Electronics VolE85-A(12),pp.2693-2700 (Collaboration)
40.	2002/06	Article	Comparision of decision diagrams for multiple-output logic functions International Workshop on Logic and　Synthesis (IWLS2002)
41.	2002/05	Article	Representations of logic functions using QRMDDs IEEE Proc. of 32nd International Symposium on Multiple-Valued Logic (ISMVL-2002) (Collaboration)
42.	2002/01	Article	A Method for Storing Fail Bit Maps in Burn-in Memory Testers Proc. of the The First IEEE International Workshop on Electronic Design, Test and Applications (Collaboration)
43.	2001/12	Article	Compact BDD representations for multiple-output functions and their applications to embedded system IFIP VLSI-SOC'01 (Collaboration)
44.	2001/10	Article	Bi-partition of shared binary decision diagrams SASIMI-2001 (Collaboration)
45.	2001/09	Article	Realization of multiple-output functions by reconfigurable cascades IEEE Proc. of International Conference on Computer Design :VLSI in Computers & Processors (ICCD-2001) (Collaboration)
46.	2001/06	Article	A cascade realization of multiple-output function for reconfigurable hardware International Workshop on Logic and Synthesis (IWLS01), (Collaboration)
47.	2000/06	Article	An Algorithm for Storing Fail-Bitmaps of Megabit RAMs pp.59-67 (Collaboration)
48.	2000/01	Article	A Hardware Smulation Engine Based on Decision Diagrams IEEE,IEICE,IPSJ,ACMProc. of Asia and Aouth Pacific Design Automation Conference 2000 pp.73-76 (Collaboration)
49.	2000	Article	Implementation of Multiple-Output Logic Functions based on PQMDDs Proc of International Symposium on Multiple Valued Logic (Collaboration)
50.	1999/01	Article	Realization of Regular Ternary Logic Functions using Double-Rail Logic Proc.of ASP-DAC'99 pp.372 (Collaboration)
51.	1998	Article	On Properties of Kleene TDDS IEICE Trans INF and Systems E81-D(7) (Collaboration)
52.	1997/11	Article	On Decomposition of Kleene TDDS IEEE Proc.of 6th Asian Test Symposium pp.417(234-239) (Collaboration)
53.	1997/01	Article	On Properties of kleene TDDs IEICE , IPSJ , ACM , and IEEEProc.Of ASP-DAC'97 pp.473-476 (Collaboration)
54.	1989	Article	Maximum PLA folding using inverters Scripta Technica,IncSystems and Computers in Japan Vol.20 No.4,pp.1-8 (Collaboration)
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■ Conference Presentations

1.	2023/09/23	Lower Bonds on the Number of Compound Variables for Index Generation Functions
2.	2023/01/07	A Method to Estimate Chord Progressions in Music Using n-grams and Rule Processing
3.	2023/01/07	A Strategy for Stock Tradingusing Machine Learning
4.	2023/01/07	Feature Reduction in Classfication Functions Using Decision Trees

■ Academic Qualifications

1.	2001/10～2012/09	Department of Human Development and Education, Faculty of Liberal Arts, The University of the Air, Graduated,
2.	1984/04～1987/03	〔Doctorial Course (2nd Semester)〕, Graduate School, Division of Engineering, Meiji University, Completed,
3.	1982/04～1984/03	〔Doctorial Course (2nd Semester)〕, Graduate School, Division of Engineering, Meiji University, Completed,
4.	～1982/03	Faculty of Engineering, Meiji University, Graduated,

■ Career History

2008/04～

Professor

■ Internal Committee Positions

2019/04/01～2021/03/31

Deputy Director, Research Extension and Intellectual Property Headquarters

■ Academic Associations Membership

1.		IEICE
2.		IEEE Computer Society

■ Research Topics, Consignment Studies & KAKENHI Researches

1.	2000	Reconfigurable architecture (Key Word : reconfigurable,CAD,FPGA)
2.	2003	Embedded software (Key Word : "embedded software,,")
3.	1996	representation of logic functions (Key Word : "logic function,,")

■ Exhibitions, Concerts & Competitions

2019/08/24～2019/08/24

CQ EV Mini-cart Race (Sodegaura Forest Raceway)

■ Current Specialized Field

Computer system, Computer system, Electron device and electronic equipment