Faculty Database - Tsutsumi Toshiyuki

Books and Papers

Conference Presentations

Academic Qualifications

Research Topics, Consignment Studies & KAKENHI Researches

Current Specialized Field

（Last updated : 2015-02-14 17:08:48.539）

Tsutsumi Toshiyuki
Department Undergraduate School , School of Science and Technology

Position Professor

■ Books and Papers

1.	2009/01	Article	"Fault Effect of Open Faults Considering Adjacent Signal Lines in a 90 nm IC" Proceedings of "22nd International Conference on VLSI Design" (Collaboration)
2.	2009/01	Article	PAPER ID=93, "A Novel Approach for Improving the Quality of Open Fault Diagnosis" Proceedings of "22nd International Conference on VLSI Design" (Collaboration)
3.	2008/10	Article	"Study of Quantum Effects on Backscattering Phenomenon from Drain Region of Double Gate MOSFET" 2008 International Microprocesses and Nanotechnology Conference pp.29D-9-21, pp.186-187. (Collaboration)
4.	2008/09	Article	"Compact Model for DG MOSFETs and its Modular Structure Implemented in Verilog-A" Proceedings of "IEEE Workshop on Compact Modeling", pp.pp.73-78. (Collaboration)
5.	2008/09	Article	"Suppression of Effect of Backscattering from Drain Region on Double-Gate Metal-Oxide-Semiconductor Field-Effect Transistor Characteristics" Japanese Journal of Applied Physics 47(6),pp.4980-4984 (Collaboration)
6.	2008/07	Article	"Fault Analysis of Interconnect Opens in 90nm CMOS ICs with Device Simulator" Proceesings of "The 23rd International Technical Conference on Circuits/Systems, Computers and Communications" (ITC-CSCC2008) pp.249-252 (Collaboration)
7.	2008/06	Article	"Comparison of Four-terminal DG MOSFET Compact Model with Thin Si channel FinFET Devices" Technical Proceedings of the 2008 NSTI-Nanotech 208 3,pp.861-864 (Collaboration)
8.	2008/05	Article	"Construction of a Compact Modeling Platform and Its Application to the Development of Multi-Gate MOSFET Models for Circuit Simulation" Technical Proceedings of the 2008 NSTI-Nanotech 208, 3,pp.764-769 (Collaboration)
9.	2008/03	Article	"Suppression of Intrinsic Delay Variation in FPGAs using Multiple Configurations" ACM Transactions on Reconfigurable Technology and Systems (TRETS), Volume 1, Issue 1, (March 2008), pp.3.1-3.31 (Collaboration)
10.	2008/01	Article	"Construction of a Compact Modeling Platform and Its Application to the Development of Multi-Gate MOSFET Moddels for Circuits Simulation" The Proceedings of The 5th International Workshop on Comact Modeling (IWCM 2008), pp.1-4. (Collaboration)
11.	2008/01	Article	"Double-Gate MOSFET Compact Model ans its implementation in Verilog-A" The Proceedings of The 5th International Workshop on Comact Modeling (IWCM 2008), pp.17-23. (Collaboration)
12.	2007/12	Article	"Optimization of the Body Bias Voltage Set (BBVS) for Flex Power FPGA" IEICE Transactions on Information and Systems, Vol.E90-D, No.12 December 2007, pp.1947-1955 (Collaboration)
13.	2007/12	Article	"Power Configurable Block Array Connected in Series as First Prototype Flex Power FPGA Chip" ICFPT2007, International Conference on Field-Programmable Technology 2007, Poster P2-5, 1-4244-1472-5/07. (Collaboration)
14.	2007/11	Article	"Pleliminary Study of Suppresson of Backscattering Phenomenon from Drain Region on Double Gate MOSFET's Characteristics" MNC2007, Microprocesses and Nanotechnology 2007, 2007 International Microprocesses and Nanotechnology Conference, 6A-4-31, pp.114-115. (Collaboration)
15.	2007/10	Article	"Clues for Modeling and Diagnosing Open Faults with Considering Adjacent Lines" The Proceedings of ATS2007 (The 2007 IEEE 16th Asian Test Symposium), pp.39-44 (Collaboration)
16.	2007/09	Article	"Backscattered Electrons from a Drain Region in a Silicon Decanano Diode" Japanese Journal of Applied Physics, Part 1, Vol. 46, No. 9B, 2007, pp. 6208-6212 (Collaboration)
17.	2007/09	Article	"Test Generation and Diagnostic Test Generation for Open Faults with Considering Adjacent Lines" The Proceedings of DFT2007 (The 22nd IEEE International Symposiumon Defect and Fault Tolerance in VLSI Systems), pp.243-251 (Collaboration)
18.	2006/10	Article	"Designing DG MOSFET's Compact Model" Proceesings of the 2006 China-Ireland International Conference on Information and Communications Technologies( CIICT06), pp. 258-261, p.447 pp.256-251, 447 (Collaboration)
19.	2006/10	Article	"Evaluation of Backscattering Effect on Drain Current in a Silicon Decanano Diode" MNC2006, Microprocesses and Nanotechnology 2006, 2006 International Microprocesses and Nanotechnology Conference, 26C-7-22, pp.140-141. pp.140-141 (Collaboration)
20.	2006/09	Article	"Analysis of Backscattering Phenomenon from Drain Region in Silicon Decanano Diode" Japanese Journal of Applied Physics, Part 1 45(9A),pp.6786-6789 (Collaboration)
21.	2006/09	Article	「複数の回路構成情報を用いたチップ内ばらつきを有するFPGAの歩留まり向上手法の提案」(RECONF2006-25) 電子情報通信学会技術研究報告 RECONF2006-20〜26(リコンフィギャラブルシステム)
22.	2006/04	Article	"Four-Terminal Doubel-Gate Logic for LSTP Applications below 32-nm Technology Node" ICICDT-2006 Proceedigs pp.92-95, ICICDT: International Conference on Integrated Circuits Design and Technology pp.92-95
23.	2006/01	Article	"Compact Model for Four-Terminal DG MOSFET" Extended Abstracts of The 3rd International Workshop on Compact Modeling, IWCM'06, pp.15-21 pp.pp.15-21 (Collaboration)
24.	2005/12	Article	"Future Devices Expand FPGA into Another Dimension - a Flex Power FPGA case -" Extended Abstracts of International Symposium on Advanced Reconfigurable Systems, pp.20-31 pp.pp.20-31 (Collaboration)
25.	2005/12	Article	"Overview of Flex Power VPR and it's Vth Assignment Algorithm" Extended Abstracts of International Symposium on Advanced Reconfigurable Systems, Non-Printed (Collaboration)
26.	2005/10	Article	"Analysis of Backscattering Phenomenon from Drain Region in a Silicon Nanodiode" MNC2005, Microprocesses and Nanotechnology 2005, 2005 International Microprocesses and Nanotechnology Conference, 28B-10-2, pp.262-263. pp.pp.262-263 (Collaboration)
27.	2005/04	Article	"Compact Model for Ultra-Short Channel Four-Terminal DG MOSFETs for Exploring Circuit Characteristics" NANOTECH 2005 Volume 2, Technical Proceedings of the 2005 Nanotechnology Conferech and Trade show, pp. 183-186 2,pp.pp. 183-186 (Collaboration)
28.	2005/04	Article	"Device Parameter Extraction from Fabricated Double-Gate MOSFETs" NANOTECH 2005 Volume 2, Technical Proceedings of the 2005 Nanotechnology Conferech and Trade show, pp. 187-190 2,pp.pp. 187-190 (Collaboration)
29.	2004/08	Article	"Preliminary Evaluation of Flex Power FPGA: A Power Reconfigurable Architecture with Fine Granularity" IEICE Transactions on Information and Systems E87-D(08),pp.pp.2004-2010 (Collaboration)
30.	2004/06	Article	"4-Terminal FinFETs with High Threshold Voltage Controllability" Conference Digest of Device Research Conference pp.207-208 (Collaboration)
31.	2004/04	Article	"Can A Cool Chip Be Hot? Yes, Flex Power FPGA Can." Cool Chips VII Proceedings 1,pp.77 (Collaboration)
32.	2004/04	Article	"Can A Cool Chip Be Hot? Yes, Flex Power FPGA Can." Cool Chips VII Proceedings 1,pp.49-57 (Collaboration)
33.	2004/03	Article	"Improved Compact Model for Four-Terminal DG MOSFETs" NANOTECH 2004 Volume 2,Technical Proceedings of the 2004 Nanotechnology Conferech and Trade show,Defense Advanced Research Projects Agency (DARPA) pp.159-16
34.	2004/02	Article	"Preliminary Performance Analysis of Flex Power FPGA a Power Reconfigurable Device with Fine Granularity" The Proceedings of FPGA2004:ACM/SIGDA Twelfth ACM International Symposium on Field-Programmable Gate ACM SIGDA pp.57 (Collaboration)
35.	2004/01	Article	"XMOS Compact Modeing and its Important Role in Vertically Integrated Novel Device Reseach The Proceedings of ASP-DAC 2004(Asia and South Pacific Design Automation Conference 2004),IEEE Electron Devices Society pp.pp14-17 (Collaboration)
36.	2004	Article	"Cross-Sectinal Channel Shape Dependence of Short-Channel Effects in Fin-Type Double-Gate Metal Oxide Semiconductor Field-Effect Transistors" Japanese Journal of Applied Physics, Part 1 43(4B),pp.2151-2155 (Collaboration)
37.	2003/12	Article	"Flexible threshold voltage FinFETs with independent double gates and an ideal rectangular cross-section Si-Fin channel 2003 IEEE IEDM(International Electron Devices Meeting),IEDM '03 Technical Digest,the IEEE Electron Devices Society pp.pp986-989 (Collaboration)
38.	2003/12	Article	"Systematic Electrical Characteristics of Ideal Rectangular Cross Section Si-Fin Channel Double-Gate MOSFETs Fabricated by a Wet Process" IEEE Transactions on Nanotechnology,The IEEE Electron Devices Society Vol.2(No.4),pp.pp198-204 (Collaboration)
39.	2003/09	Article	"An Experimental Study of The Cross-Sectional Channel Shape Dependence of Shot-Channe Effects in Fin-Type Double-Gate MOSFETs" Extended Abstracts of the 2003 International Coference on Solid State Dvices and Materials,The Japan Society of Applied Physics pp.pp284-285 (Collaboration)
40.	2003/07	Article	"Ideal Rectangular Cross-Section Si-Fin Channel Doble-Gate MOSFETs Fabricated Using Orientation-Dependent Wet Etching" IEEE Electron Devices Lette,The IEEE Electron Devices Society Vol.24(No.7),pp.pp484-486 (Collaboration)
41.	2003/06	Article	"Electrical Property of Ideal Rectangular Si-Fin Channel Double-Gate MOSFETs" Abstracts of 2003 Silicon Nanoelectronics Workshop,A Satellite Conference of the VLSI Symposium,The IEEE Electron Devices Society pp.pp64-65 (Collaboration)
42.	2003/06	Article	Fin-Type Double-Gate Metal-Oxide and Semiconductor Field-Effect Transistors Fabricated by Orientation-Dependent Etching and Electron Beam Lithography Japanese Journal of Applied Physics,The IEEE Electron Devices Society Part1,Vol.42(No.6B),pp.pp4142-4146 (Collaboration)
43.	2003/04	Article	"Multi-Fin Double-Gate MOSFET Fabricated by Using(110)-Oriented SOI Wafers and Orientation-Dependent Etching" The Proceedings of the 203rd Meeting of the Electrochemical Society,The Electrochemical Society pp.p876 (Collaboration)
44.	2001/10	Article	Electrical and Geometrical Properties of a Quantum Nanowire Device Fabricated by an Inorganic EB Resist Process The Japan Society of Applied Physics, the IEEE Electron Devices SocietyDigest of Papers: 2001 International Microprocess and Nanotechnology Conference,Kunibiki Messe, Matsue-shi, Simane, Japan pp.70-71 (Collaboration)
45.	2001/03	Article	'Evaluation of Si Nanowires through Device Characteristics and Improvement in Unifomity of Si Nanowire Width using Self-Iimiting Oxidatin' The Institute of Electrical Engineers of JapanThe transactions of The Institute of Electrical Engineers of Japan [A publication of Electronics, Information and System Society] pp.515-523 (Collaboration)
46.	2000/11	Article	'Evaluation of Si Nanowires by Device Characteristics and Improvement in Unniformity of Si Nanowire Width Using Self-Iimiting Oxidation'(国際学会議事録) Research and Development Association for Future Electron Devices(FED)Extended Abstracts of 4th International Workshop on Quantum Functional Devices, pp.97-98 (Collaboration)
47.	2000/11	Article	'Fabrication technology of a Si nanowire memory transistor using an inorganic electron beam resist process'(学会誌) The American Vacuum Society, the American institute of PhysicsJournal of Vacuum Science & Technology B Vol.18 №6,pp.2640-2645 (Collaboration)
48.	2000/11	Article	'Properties of Si nanowire devices fabricated by using an inorganic EB resist process'(学術雑誌) Academic PressSuperlattices and Microstructures Vol.28 №5/6,pp.453-460 (Collaboration)
49.	2000/11	Article	'Spectroscopic Ellipsometry Studies on Ultrathin hydrogenated Amorphous Silicon Films Prepared by Themal Chemical Vapor Deposition'(学会誌) The American Vacuum Society, the American Institute of PhysicsJapanese Journal of Applied Physics Part1, Vol.39 №11,pp.6196-6201 (Collaboration)
50.	2000/10	Article	'Development of Silicon Nanowire Devices'
51.	2000/09	Article	'Visualization of longitudinal Vibrations of an Elastic Rod by Using a Laser' Physics Education Society of JapanButuri Kyoiku pp.310-314 (Collaboration)
52.	2000/07	Article	'Fabrication Technology of Si Nanodot Nanowire Memory Transistors Using an Inorganic EB Resist Process'(国際学会議事録) The Japan Society of Applied Physics, the IEEE Electron Devices SocietyDigest of Papers: 2000 International Microprocess and Nanotechnology Conference pp.182-183 (Collaboration)
53.	2000/07	Article	'Single electron memory characteristic of silicon nanodot nanowire transistor'(学会誌) The Institution of Electronics EngineersThe IEE Electronics Letters Vol.36 №15,pp.1322-1323 (Collaboration)
54.	2000/06	Article	'Fabrication of Si Nanodot Nanowire Memory Transistors and their Properties'(国際学会議事録) The IEEE Electron Devices Society, the Japan Society of Aplied PhysicsAbstracts of 2000 Silicon Nanoelectronics Workshop, A Satellite Conference of the VLSI Symposium pp.77-78 (Collaboration)
55.	1999/12	Article	A Method of Quantum Transport for Deca-nano Electron Devices
56.	1999/10	Article	Development of Si and compound semiconductor ultra-small FETs
57.	1999/09	Article	Plane-view observation technique of silicon nanowires by transmission electron American Vacuum SocietyJournal of Vacuum Science & Technology B Vol.17, No.5,pp.1897-1902 (Collaboration)
58.	1999/06	Article	An Experimental 40-nm Gate Length 4-nm-Thick SOI n-MOSFET(国際会議) The Japan Society of Applied Physics and The JapanThe IEEE Electron Device Society1999 Silicon Nanoelectronics Workshop Abstracts, Kyoto pp.72-73 (Collaboration)
59.	1999/06	Article	High Suppression of the Short-Channel Effect in Ultrathin SOI n-MOSFETs(国際会議) The IEEE Electron Device SocietyProceedings of the 57th Annual Device Reseach Conference, UCSB pp.32-33 (Collaboration)
60.	1999/05	Article	Highly Suppressed Threshold Voltage Roll-off Characteristics of the 4 nm-Thick SOI n-MOSFETs in the 40-135 nm Gate Length Regime(国際会議) The Electrochemical SocietyProceedings of the 9th International Symposium on SOI Technology and Devices, Seatle pp.260-265 (Collaboration)
61.	1999/04	Article	Fabrication of 40-150 nm Gate Length Ultrathin n-MOSFETs using Epitaxial Layer Transfer SOI Wafers The Japan Society of Applied Physics,Japanese Journal of Applied Physics Vol.38 Part1 No.4B,pp.2492-2495 (Collaboration)
62.	1999/02	Article	Highly Suppressed Short-Channel Effects in Ultrathin SOI n-MOSFETs The IEEE Electron Devices SocietyIEEE transactions iof Electron Devices Vol.47 No.2,pp.354-359 (Collaboration)
63.	1999/01	Article	Fabrication Technology of Ultrafine SiO2 masks and Si nanowires using oxidation of vertical sidewalls of a Poly-Si layer Journal of Vacuum Science & Technology B Vol.17, No.1,pp.77-81 (Collaboration)
64.	1998/09	Article	Fabrication of 40-150nm Gate Length Ultrathin n-MOSFETs using ELTRAN SOIWafers(国際会議) Extended Abstracts of International Conference on Solid State Devices and Materials, Hiroshima pp.320-321 (Collaboration)
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■ Conference Presentations

1.	2005/09	"Analysis of near-ballistic eletron transport in a silicon nanodiode"
2.	2005/09	"Early Development of Microproccessor Design Education System MEMES-DESIGN"
3.	2000/09	'Electric Properties of Silicon Nanowire Memory Transistor using Inorganic EB Resist'
4.	2000/04	'Spectroscopic Ellipsometry for the Characterization of the Morphology of Ultra-thin Thermal CVD Amorphous and Nanocrystalline Silicon Thin Films'
5.	2000/03	'Structural Studies of ultra-thin amorphous silicon and nanocrystalline silicon by Spectroscopic Ellipsometry'
6.	2000/03	Fablication of Si Nanowire Memory Transistors Using an Inorganic EB Resist
7.	1999/09	Evaluation of Silicon Nanowires fabricated by Self-limiting Oxidation Effect
8.	1999/03	Characteristics of ultra-short channel, 4mn-thick ultrathin SOI n-MOSFET
9.	1999/03	Plane-view Observation Technique of Silicon Nanowires by Transmission Electron Microscopy
10.	1998/09	Fabrication Technology of Ultra-fine Mask using Side Oxidation of Poly-Si Layer
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■ Academic Qualifications

1.	～2000	Graduate School, Division of Science and Engineering, Meiji University,
2.	～1988	Graduate School, Division of Engineering, Meiji University,

■ Research Topics, Consignment Studies & KAKENHI Researches

1.		Research of device simulation (Key Word : ",,")
2.		Research on the Nanoscale Silicon Devices (Key Word : )
3.		Study on Ultra-small Silicon Devices (Key Word : ",,")
4.	2001	Research on Flex Power FPGA (Key Word : "Low Power,FPGA,")
5.	2001	Research on system level LSI design technology (Key Word : "SoC,,")

■ Current Specialized Field

Computer system, Electron device and electronic equipment